This figure uses a series of squares inside of a large rectangle in order to illustrate host architecture. The large rectangle itself is designated as the host. Inside the rectangle, starting at the top, we see two squares positioned side-by-side. The square on the left is labeled "CPU" and the square on the right is labeled "Memory." The CPU is associated with a four-layer protocol stack, in which the layers are labeled (from top to bottom): Application, Transport, Network, Link. The CPU and Memory boxes each have vertical lines that extend downward and connect with a horizontal line. The horizontal line is labeled "Host bus (e.g., PCI)."

Beneath these two boxes is a smaller rectangle, designated as the "Network adapter." Inside the rectangle are two boxes positioned one on top of the other. The top box is labeled "Controller" and the bottom box is labeled "Physical transmission." These boxes are both associated with a single two-layer protocol stack, in which the layers are (from top to bottom): "Link" and "Physical."

A blue line points back and forth between CPU and Controller, between Controller and Physical transmission, and between Physical transmission and the bottom of the host.