Long description

Part (a): Two C P U vertical blocks and one Shared memory vertical block labeled M are connected using a bus. Part (b): Two C P U blocks and one Shared memory block labeled M are connected using a bus. A cache horizontal highlighted block is shown inside the CPU block. Part (c): Two C P U blocks and one Shared memory block labeled M are connected using a bus. A cache block is shown inside the C P U block. Two private memory vertical blocks are connected above the C P U blocks.