Long description

Figure a: The blocks labeled CPU, Memory, and I slash O are arranged from left to right. Connection lines labeled all addresses (memory and I slash O) go here, from the bottom of each line are connected to a bus.

Figure b: The blocks labeled CPU, Memory, and I slash O are arranged from left to right and connected from the bottom to a bus. Here the C P U block and memory block is connected by a bus which is labeled C P U reads and writes of memory go over this high bandwidth bus. The text labeled This memory port is to allow I slash O devices access to memory points to the memory block.